Digital imagers have become popular features in various electronic devices. Typically, a digital imager includes an array of imager pixels or cells with each of the pixels including a photoconversion device (e.g. a photogate, photoconductor, or photodiode). In a Complementary Metal Oxide Semiconductor (CMOS) imager, a readout circuit is connected to each imager pixel which typically includes a source follower output transistor. The photoconversion device converts photons to electrons which are typically stored at a floating diffusion region connected to the gate of the source follower output transistor. A charge transfer device (e.g., a pass transistor) can he included for transferring charge from the photoconversion device, also known as a charge accumulation region, to the floating diffusion region, also known as a charge collection region. In addition, such imager pixels typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. Furthermore, the output signal of the source follower transistor is gated by a row select transistor.
CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing patents are herein incorporated by reference in their entirety.
FIG. 1 shows one example of an imager pixel 10 of a conventional CMOS imager. A photodiode 12 or a charge accumulation region is comprised of regions 14, 16 which are opposite doping types, creating a p-n junction. When incident light strikes the photodiode 12, electron/hole pairs are generated in the p-n junction of the photodiode 12. The generated electrons are collected in the n-type region 16 of the photodiode 12. The photo charge is transferred from the initial charge accumulation region to a charge collection region, typically a floating diffusion region 18 via a transfer transistor 20, as illustrated in FIG. 1. The collected charge at floating diffusion region 18 is typically converted to a pixel output voltage VOUT by controlling the gate of a source follower transistor 22.
In operations, a row select transistor 24 is activated by row select signal RS and connects the imager pixel 10 to a column line 26. A reset transistor 28 is typically turned on by a reset signal RESET and the residual collected charge in the floating diffusion region 18 is reset to a predetermined voltage (egg. Vdd). Integration of light and accumulation of electrons at photodiode 12 is conducted at least during the reset period and prior to the application of a transfer gate voltage signal TX. The transfer gate voltage signal TX is then applied to the gate of the transfer transistor 20 to cause the accumulated charge in the photodiode 12 to transfer to the collection or floating diffusion region 18.
As illustrated, the collection or floating diffusion region 18 is electrically connected to the gate of a source follower transistor 22, the output of which is selectively applied to the column line 26 by row select transistor 24. The reset transistor 28 selectively resets the collection or floating diffusion region 18 to a predetermined voltage by coupling a voltage Vdd to the collection or floating diffusion region 18 during a reset period which precedes or follows a charge accumulation or integration period.
While a four-transistor (4T) imager pixel design provides a separate reset transistor 28 to reset the collection or floating diffusion region 18 to a known potential, there is an ever increasing desire to minimize the number of transistors used in an imager pixel to reduce pixel cell size, increase pixel density in an array and increase the proportion (e.g., fill factor) of the charge accumulation region (e.g., photodiode) with the overall size of the imager pixel. Furthermore, there is also a further desire to simplify overall imager pixel design and fabrication complexity.